The present invention relates generally to integrated circuit memory devices, and more specifically to integrated circuit memory devices which undergo stress testing.
Stress testing of integrated circuit memory devices having redundant and non-redundant elements is a valuable technique used to analyze the reliability of the device. Stress testing enables a plurality of rows and/or columns of the memory device, and it is desirable to enable all rows and columns of the memory device simultaneously so that these elements are stressed in the most efficient manner. Enhanced stress test modes which provide substantial benefits such as decreased burn-in time, decreased FIT rate, and improved yield have been defined. For example, copending U.S. Pat. application Ser. No. 08/172,854, titled "Stress Test Mode", Docket No.: 93-C-56, filed Dec. 22, 1993, discusses some of these benefits. Such enhanced stress test modes tend to accelerate oxide failures of the device being stressed and thus create yield fallout normally not seen until burn-in of the device. Additionally, optimal device reliability may be obtained when the cells of a memory device, redundant and non-redundant, are equally subjected to stress testing.
When a memory device is stressed tested during the manufacturing flow will determine whether all cells of the device are stressed equally. If the memory device is stressed at prelaser or some other pre-repair step, the redundant elements are not yet enabled, and hence only the non-redundant elements are stressed at that time. Then, when the redundant elements are enabled at postlaser or some other post-repair step, the device would be stressed again to verify all the elements of the device have been stressed for maximum fault coverage. For example, a fast 1 Meg SRAM which has in excess of 20,000 redundant elements would need to be stress tested after the redundant elements are enabled at postlaser to ensure reliability of the redundant elements. As a result of performing two stress tests, one at prelaser and the second at postlaser, the non-redundant elements of the device are stressed twice while the redundant elements are stressed only once. From a reliability standpoint, it is undesirable to stress the redundant and non-redundant elements of the device unevenly in this manner. Also, performing multiple stress tests requires more time and is thus more costly.
One possible solution is to perform stress testing of the device only at postlaser so that stress test time is reduced and all elements of the device, redundant and non redundant, are equally stressed. However, postlaser stress testing, unlike prelaser stress testing, does not allow yield fallout recovery. Yield fallout from postlaser stress testing can be significant and may be greater than 3% of the device depending on the density, process maturity, and processing of the memory device. Thus, while only performing stress testing at postlaser repair does not unevenly stress the device, it does have a negative impact on the potential yield recovery of the device.
Thus, there exists a current need in the art to equally stress test redundant and non-redundant elements of an integrated circuit device in such a manner that yield fallout resulting from enhanced stress test modes or otherwise may be recovered, and stress testing time may be minimized.